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Preliminary Technical Data
FEATURES
16-bit resolution with no missing codes 8-channel multiplexer with: Unipolar single ended or Differential (GND sense)/Bipolar inputs Throughput: 250 kSPS INL/DNL: 0.6 LSB typical Dynamic range: 93.5 dB SINAD: 92.5 dB @ 20 kHz THD: -100 dB @ 20 kHz Analog input range: 0 V to VREF with VREF up to VDD Reference: Internal selectable 2.5 V/4.096 V or External buffered (up to 4.096 V) External (up to VDD) Internal temperature sensor Channel sequencer, selectable 1-pole filter, BUSY indicator No pipeline delay, SAR architecture Single-supply 2.7V - 5.5 V operation with 1.8 V to 5 V logic interface Serial interface SPI(R)/QSPITM/MICROWIRETM/DSP compatible Power dissipation: 6 mW @ 5 V/100 kSPS Standby current: 1 nA 20-lead 4 mm x 4 mm LFCSP package
16-Bit, 8-Channel, 250 kSPS PulSAR(R) ADC AD7689
FUNCTIONAL BLOCK DIAGRAM
0.5V to 4.096V 0.1F REFIN Band Gap REF 0.5V to VDD 22F REF 2.7V to 5V VDD 1.8V to VIO VDD
AD7689
Temp Sensor
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND CNV MUX 1-Pole LPF Sequencer 16-Bit SAR ADC SPI Serial Interface SCK SDO DIN
Figure 1.
Table 1. Multichannel14-/16-Bit PulSAR ADC
Type 14-Bit 16-Bit 16-Bit Channels 8 4 8 250 kSPS AD7949 AD7682 AD7689 500 kSPS ADC Driver ADA4841-X ADA4841-X ADA4841-X
AD7699
GENERAL DESCRIPTION
The AD7689 is an 8-channel 16-bit, charge redistribution successive approximation register (SAR), analog-to-digital converter (ADC) that operates from a single power supply, VDD. The AD7689 contains all of the components for use in a multichannel, low power, data acquisition system including: a true 16bit SAR ADC with no missing codes; an 8-channel, low crosstalk multiplexer useful for configuring the inputs as single ended (with or without ground sense), differential or bipolar; an internal low drift reference (selectable 2.5V or 4.096V) and buffer; a temperature sensor; a selectable 1-pole filter; and a sequencer useful when channels are continuously scanned in order. The AD7689 uses a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput. The AD7689 is housed in a tiny 20-lead LFCSP with operation specified from -40C to +85C.
APPLICATIONS
Battery-powered equipment Medical instruments Mobile communications Personal digital assitants Data acquisition Seismic data acquisition systems Instrumentation Process Control
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD7689 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 11 Overview...................................................................................... 11 Converter Operation.................................................................. 11 Transfer Functions...................................................................... 12
Preliminary Technical Data
Typical Connection Diagram ................................................... 12 Configuration Register, CFG .................................................... 13 Analog Inputs ............................................................................. 13 Driver Amplifier Choice ........................................................... 14 Voltage Reference Output/Input .............................................. 15 Power Supply............................................................................... 16 Supplying the ADC from the Reference.................................. 16 Digital Interface.......................................................................... 16 Without Busy Indicator ............................................................. 17 With Busy Indicator................................................................... 18 Application Hints ........................................................................... 19 Layout .......................................................................................... 19 Evaluating AD7689 Performance............................................. 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
Rev. PrC | Page 2 of 20
Preliminary Technical Data SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Conditions/Comments Min 16 0 -VREF/2 -0.1 -0.1 VREF/2 - 0.1 VREF/2 TBD 1 Typ Max
AD7689
Unit Bits V V
Analog Input CMRR Leakage Current at 25C Input Impedance1 THROUGHPUT Conversion Rate Transient Response ACCURACY No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Gain Error3 Gain Error Match Gain Error Temperature Drift Offset Error3 Offset Error Match Offset Error Temperature Drift Power Supply Sensitivity AC ACCURACY4 Dynamic Range Signal-to-Noise Signal-to-(Noise + Distortion) Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Intermodulation Distortion6 SAMPLING DYNAMICS -3 dB Input Bandwidth Aperture Delay
1 2 3
Unipolar mode Bipolar mode Positive input, unipolar and bipolar mode Negative or COM input, unipolar mode Negative or COM input, bipolar mode fIN = 250 kHz Acquisition phase
+VREF +VREF/2 VREF + 0.1 +0.1 VREF/2 + 0.1
dB nA
VDD = 4.096V to 5.5 VDD = 2.5V to 4.096V Full-scale step
0 1
250 200 1.8
kSPS s Bits LSB2 LSB LSB LSB LSB ppm/C LSB LSB ppm/C ppm dB5 dB dB dB dB dB dB dB MHz ns
16 -2 -1 REF = VDD = 5 V -30
-5
VDD = 5 V 5%
0.6 0.25 0.5 0.5 TBD 0.3 0.5 TBD 0.3 1 93.5 92.5 88.5 92.5 88.5 -100 110 -117 115
+2 +1.5 +30
+5
fIN = 20 kHz, VREF = 5V fIN = 20 kHz, VREF = 2.5V fIN = 20 kHz, VREF = 5V fIN = 20 kHz, VREF = 2.5V fIN = 20 kHz fIN = 20 kHz fIN = 100 kHz on adjacent channel(s)
Selectable VDD = 5V
0.425
1.7 2.5
See the Analog Inputs section. LSB means least significant bit. With the 5 V input range, one LSB is 76.3 V. See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 With VREF = 5 V, unless otherwise noted. 5 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 6 fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at -7 dB below full scale.
Rev. PrC | Page 3 of 20
AD7689
Table 3.
Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Long-Term Drift Turn-On Settling Time EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE SENSOR Output Voltage1 Temperature Sensitivity DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format2 Pipeline Delay3 VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current4, 5 Power Dissipation Conditions/Comments For 4.096 V output, @ 25C For 2.5 V output, @ 25C -40C to +85C VDD = 5 V 5% 1000 hours CREF = 22 F REF Input REFIN Input (Buffered) 250 kSPS, REF = 5V @ 25C Min 4.086 2.490
Preliminary Technical Data
VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Typ 4.096 2.500 TBD TBD 50 TBD
Max 4.106 2.510
Unit
V V ppm/C ppm/V ppm ms
0.5 0.5 50 283 1
VDD + 0.3 4.096
V V A mV mV/C
-0.3 0.7 x VIO -1 -1
+0.3 x VIO VIO + 0.3 +1 +1
V V A A
ISINK = +500 A ISOURCE = -500 A Specified performance Specified performance VDD and VIO = 5 V, 25C VDD = 5V , 100 kSPS throughput VDD = 5V , 250 kSPS throughput VDD = 5V , 250 kSPS throughput internal reference and buffer enabled
0.4 VIO - 0.3 2.3 2.3 1.8 1 6 15 18.5 5.5 VDD + 0.3 VDD + 0.3 50
V V V V V nA mW mW mW
Energy per Conversion TEMPERATURE RANGE6 Specified Performance
1 2
50 TMIN to TMAX -40 +85
nJ C
The output voltage is internal and present on a dedicated multiplexer input. Unipolar mode: serial 16-bit straight binary Bipolar mode: serial 16-bit 2's complement. 3 Conversion results available immediately after completed conversion. 4 With all digital inputs forced to VIO or GND as required. 5 During acquisition phase. 6 Contact an Analog Devices sales representative for the extended temperature range.
Rev. PrC | Page 4 of 20
Preliminary Technical Data TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted. Table 4. 1
Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV Low to SDO D15 MSB Valid VIO Above 4.5 V VIO Above 2.7 V VIO Above 2.3 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV High to SCK Low DIN Valid Setup Time from SCK Falling Edge DIN Valid Hold Time from SCK Falling Edge
1
AD7689
Symbol tCONV tACQ tCYC tCNVH tSCK tSCKL tSCKH tHSDO tDSDO
Min 0.5 1.8 4 10 15 7 7 4
Typ
Max 2.2
Unit s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
14 15 16 17 tEN 15 18 22 25 10 4 4
tDIS tCSCK tSDIN tHDIN
See Figure 2 and Figure 3 for load conditions.
Rev. PrC | Page 5 of 20
AD7689
Table 5. 1
Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV Low to SDO D15 MSB Valid VIO Above 2.7 V VIO Above 2.3 V CNV High or Last SCK Falling Edge to SDO High Impedance CNV High to SCK Low SDI Valid Setup Time from SCK Falling Edge SDI Valid Hold Time from SCK Falling Edge
1
Preliminary Technical Data
VDD = 2.5 V to 4.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Symbol tCONV tACQ tCYC tCNVH tSCK tSCKL tSCKH tHSDO tDSDO
Min 0.7 1.8 5 10 25 12 12 5
Typ
Max 3.2
Unit s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
24 30 35 tEN 18 22 25 10 5 4
tDIS tCSCK tSDIN tHDIN
See Figure 2 and Figure 3 for load conditions.
500A
IOL
TO SDO CL 50pF 500A IOH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
70% VIO 30% VIO
tDELAY
2V OR VIO - 0.5V1 0.8V OR 0.5V2
tDELAY
2V OR VIO - 0.5V1 0.8V OR 0.5V2
-003
1. 2V IF VIO ABOVE 2.5V, VIO - 0.5V IF VIO BELOW 2.5V. 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
Rev. PrC | Page 6 of 20
-002
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Analog Inputs INn,1 COM1 REF, REFIN Supply Voltages VDD, VIO to GND VDD to VIO DIN, CNV, SCK to GND SDO to GND Storage Temperature Range Junction Temperature JA Thermal Impedance (MSOP-10) JC Thermal Impedance (MSOP-10)
1
AD7689
Rating GND - 0.3 V to VDD + 0.3 V or 130 mA GND - 0.3 V to VDD + 0.3 V -0.3 V to +7 V 7 V -0.3 V to VIO + 0.3 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 200C/W 44C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
See Analog Inputs section.
Rev. PrC | Page 7 of 20
AD7689 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
20 19 18 17 16 VDD IN3 IN2 IN1 IN0
PIN 1 INDICATOR
Preliminary Technical Data
Figure 4. 20-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1, 20 Mnemonic VDD Type1 P Description Power Supply. Nominally 2.5 V to 5.5 V when using an external reference, and decoupled with 10 F and 100 nF capacitors. When using the internal reference for 2.5V output, the minimum should be 2.7V. When using the internal reference for 4.096V output, the minimum should be 4.5V. Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference = 2.5V or 4.096V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096V max.) useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5V to VDD). For any reference method, this pin needs decoupling with an external a 22 F capacitor connected as close to REF as possible. See the Reference Decoupling section. Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1F capacitor. When using the internal reference buffer, apply a source between 0.5V to 4.096V which is buffered to the REF pin as described above. Power Supply Ground. Channel 4 through Channel 7 Analog Inputs. Common Channel Input. All channels [7:0] can be referenced to a common mode point of 0 V or VREF/2 V. Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the BUSY indictor is enabled. Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. Serial Data Clock Input. This input is used to clock out the data on ADO and clock in data on DIN in an MSB first fashion. Serial Data Output. The conversion result is output on this pin synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes conversion results are twos complement. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Channel 0 through Channel 3 Analog Inputs.
2
REF
AI/O
3
REFIN
AI/O
4, 5 6-9 10 11 12 13 14
GND IN4 - IN7 COM CNV DIN SCK SDO
AI AI AI DI DI DI DO
15 16 - 19
1
VIO IN0 - IN3
P AI
AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Rev. PrC | Page 8 of 20
IN4 6 IN5 7 IN6 8 IN7 9 COM 10
00000-004
VDD REF REFIN GND GND
1 2 3 4 5
TOP VIEW
15 VIO 14 SDO 13 SCK 12 DIN 11 CNV
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
2 1.5 1 0.5
DNL (LSB) 1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1
AD7689
INL (LSB)
0 -0.5 -1 -1.5 -2 0 16384 32768 CODE 49152 65536
0
16384
32768 CODE
49152
65536
Figure 5. Integral Nonlinearity vs. Code, VREF = 5V
200000 196433 180000 160000 140000 120000 COUNTS 100000 80000 60000 40000 20000 0 0 7FFC 0 7FFD 44 7FFE 7FFF 8000 8001 76 8002 0 8003 0 8004 27695 36872
Figure 8. Differential Nonlinearity vs. Code, VREF = 5V
200000
= 0.44 VREF = 5V
180000 160000 140000 120000 COUNTS 100000 80000 60000 40000 20000 0 0 7FFA 0 7FFB 784 7FFC 7FFD 50640
171449
= 0.83 VREF = 2.5V
37789
457 7FFE 7FFF 8000
1 8001
0 8002
CODE IN HEX
CODE IN HEX
Figure 6. Histogram of a DC Input at Code Center, VREF = 5V
0 -20 -40 AMPLITUDE (dB of Full Scale) -60 -80 -100 -120 -140 -160 -180
100 125 25 50 75 0
fs = 250 kSPS fIN = 10.1 kHz SNR = 91.1 dB THD = -102 dB SFDR = 103 dB SINAD = 91 dB
Figure 9. Histogram of a DC Input at Code Center, VREF = 2.5V
0 -20 -40 AMPLITUDE (dB of Full Scale) -60 -80 -100 -120 -140 -160 -180
0 25 75 100 50 125
fs = 250 kSPS fIN = 10.1 kHz SNR = 87.1 dB THD = -104 dB SFDR = 104 dB SINAD = 87 dB
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 7. 10kHz FFT, VREF = 5V
Figure 10. 10kHz FFT, VREF = 2.5V
Rev. PrC | Page 9 of 20
AD7689 TERMINOLOGY
Least Significant Bit (LSB) The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is
Preliminary Technical Data
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: ENOB = (SINADdB - 1.76)/6.02 and is expressed in bits. Channel-to-Channel Crosstalk Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a DC to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel and is expressed in dB. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25C on a sample of parts at the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25C), and TMAX. It is expressed in ppm/C as
TCVREF (ppm/C ) = VREF ( Max ) - VREF ( Min) VREF (25C) x (TMAX - TMIN ) x 106
LSB (V) =
VREF 2N
Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 12). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level 1/2 LSB above analog ground (38.14V). The unipolar offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111...10 to 111...11) should occur for an analog voltage 11/2 LSB below the nominal full-scale. The gain error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or % of full-scale range), which includes the effects of the offset error. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels.
where: VREF (Max) = maximum VREF at TMIN, T(25C), or TMAX. VREF (Min) = minimum VREF at TMIN, T(25C), or TMAX. VREF (25C) = VREF at 25C. TMAX = +85C. TMIN = -40C.
Rev. PrC | Page 10 of 20
Preliminary Technical Data THEORY OF OPERATION
IN+ SWITCHES CONTROL MSB CAP GND 32,768C 16,384C MSB 4C 2C C C LSB SW- CNV 32,768C 16,384C 4C 2C C C COMP CONTROL LOGIC LSB SW+ BUSY
AD7689
OUTPUT CODE
IN- or COM
Figure 11. ADC Simplified Schematic
OVERVIEW
The AD7689 is an 8-channel, 16-bit, charge redistribution successive approximation register (SAR), analog-to-digital converter (ADC). The AD7689 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. For example, when operating with an external reference at 1 kSPS, it consumes TBD W typically, ideal for battery-powered applications. The AD7689 contains all of the components for use in a multichannel, low power, data acquisition system including: * 16-bit SAR ADC with no missing codes * 8-channel, low crosstalk multiplexer * Internal low drift reference and buffer * Temperature sensor * Selectable 1-pole filter * Channel sequencer all of which are configured through a SPI compatible, 14-bit register. The AD7689 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency. The AD7689 uses a simple SPI interface for configuring and receiving conversion results. The AD7689 is specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 20-lead, 4mm x 4mm LFCSP that combines space savings and allows flexible configurations. It is pin-for-pin compatible with the 16-bit AD7682, AD7699 and 14-bit AD7949.
CONVERTER OPERATION
The AD7689 is a successive approximation ADC based on a charge redistribution DAC. Figure 11 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator's input are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the IN+ and IN- (or COM) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and CAP, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/32,768). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7689 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.
Rev. PrC | Page 11 of 20
-005
AD7689
TRANSFER FUNCTIONS
With the inputs configured for unipolar range (single ended, COM with ground sense, or paired differentially with IN- as ground sense), the data output is straight binary.
ADC CODE
Preliminary Technical Data
2's COMP STRAIGHT BINARY 011...111 011...110 011...101 111...111 111...110 111...101
With the inputs configured for bipolar range (COM = VREF/2, or paired differentially with IN- = VREF/2), the data outputs are two's complement. The ideal transfer characteristic for the AD7689 is shown in Figure 12 and Table 8 for both unipolar and bipolar ranges with the internal 4.096V reference.
100...010 100...001 100...000
000...010 000...001 000...000 -FSR
-FSR + 1LSB
-FSR + 0.5LSB
+FSR - 1LSB +FSR - 1.5LSB
ANALOG INPUT
-015
Figure 12. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR
1 2
Unipolar Analog Input1 VREF = 4.096 V 4.095938 V 2.048063 V 2.048 V 2.047938 V 62.5 V 0V
Digital Output Code (Straight Binary Hex) 0xFFFF3 0x8001 0x8000 0x7FFF 0x0001 0x00004
Bipolar Analog Input2 VREF = 4.096 V +2.047938 V 62.5 V 0 -62.5 V -2.047938 V -2.048 V
Digital Output Code (2's Complement Hex) 0x7FFF 0x0001 0x00004 0xFFFF3 0x8001 0x8000
With COM or IN- = 0 V or all INx referenced to GND. With COM or IN- = VREF /2. 3 This is also the code for an overranged analog input ((IN+) - (IN-) , or COM, above VREF - VGND). 4 This is also the code for an underranged analog input ((IN+) - (IN-), or COM, below VGND).
TYPICAL CONNECTION DIAGRAM
Figure 13 shows an example of the recommended connection diagram for the AD7689 when multiple supplies are available.
5V 1.8V TO VDD
V+
22F2
100nF
100nF
100nF
0 TO VREF ADA4841-X 3 V- V+
REF IN0
REFIN VDD
VIO
AD7689
DIN SCK SDO CNV 3-WIRE INTERFACE 4
INn
0 TO VREF ADA4841-X 3 0 V or VREF /2 V- COM
GND
1INTERNAL REFERNCE SHOWN. SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 22F CERAMIC CAPACITOR (X5R). 3SEE DRIVER AMPLIFIER SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. 4SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 13. Typical Application Diagram with Multiple Supplies
Rev. PrC | Page 12 of 20
-006
Preliminary Technical Data
CONFIGURATION REGISTER, CFG
The AD7689 uses a 14-bit configuration register (CFG[13:0]) for configuring the inputs, channel to be converted, 1-pole filter bandwidth, reference, and channel sequencer. The CFG is latched MSB first with DIN synchronized to SCK rising edge. At the end of conversion, the register is updated allowing the new settings to be used. There is always a one deep conversion delay regardless of when the CFG is written to; during or after conversion. Note that at power up, the CFG is undefined and a dummy conversion is required to update the register. To preload the CFG with a factory setting, hold DIN high for 1 conversion. Thus CFG[13:0] = 0x3FFF. This sets the AD7689 for: * IN[7:0] unipolar referenced to GND, sequenced in order * Full bandwidth for 1-pole filter * Internal reference/temp sensor disabled, buffer enabled * No read back of CFG Table 9 Summarizes the configuration register bit details. Each corresponding section, where necessary, highlights further details of the bits used for the specific functions. Table 9. Configuration Register Description
Bit 13 12:10 Name CFG INCC Description 0 - Keep current config settings 1 - Overwrite contents of register Input Channel Configuration 12 11 10 Function 0 0 X Bipolar differential pairs, INreferenced to VREF/2 0 1 0 Bipolar, IN0-IN7 referenced to COM = VREF/2 0 1 1 Temperature sensor 1 0 X Unipolar differential pairs, INreferenced to GND (100mV) 1 1 0 Unipolar, IN0-IN7 referenced to COM = GND (100mV) 1 1 1 Unipolar, IN0-IN7 referenced to GND (single ended) Channel Selection in binary fashion 9 8 7 Function 0 0 0 IN0 0 0 1 IN1 . . . 1 1 1 IN7 Selects BW for Low Pass Filter 0 - 1/4 of BW 1 - Full BW Reference/Buffer Selection 5 4 3 Function 0 0 0 Internal ref, REF = 2.5V output 0 0 1 Internal ref, REF = 4.096V output 0 1 0 External ref, Temp enabled 0 1 1 External ref, internal Buffer, Temp enabled 1 1 0 External ref, Temp disabled 1 1 1 External ref, internal Buf, Temp disabled 2:1 SEQ
AD7689
Channel Sequencer 2 1 Function 0 0 Disable Sequencer 0 1 Update config during sequence 1 0 Scan IN0-INn (set in CFG[9:7]) then TEMP 1 1 Scan IN0-INn (set in CFG[9:7]) Read back 0 - Read back current configuration at end of data 1- Do not read back contents of configuration
0
RB
ANALOG INPUTS
Input Configurations
Figure 14 shows the different methods for configuring the analog inputs with CFG[12:10].
CH0+ CH1+ CH2+ CH3+ CH4+ CH5+ CH6+ CH7+ IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND A- 8 CHANNELS, SINGLE ENDED CH0+ CH1+ CH2+ CH3+ CH4+ CH5+ CH6+ CH7+ COMIN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND B - 8 CHANNELS, COMMON REFERNCE
CH0+ (-) CH0- (+) CH1+ (-) CH1- (+) CH2+ (-) CH2- (+) CH3+ (-) CH3- (+)
{ { { {
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND C - 4 CHANNELS, DIFFERENTIAL
CH0+ (-) CH0- (+) CH1+ (-) CH1- (+)
{ {
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM GND D - COMBINATION
CH2+ CH3+ CH4+ CH5+ COM-
9:7
INn
6
BW
Figure 14. Multiplexed Analog Input Configuraitons
The analog inputs can be configured as: * Figure 14A, single ended referenced to system ground; CFG[12:10] = 1112. * Figure 14B, bipolar differential with a common reference point, COM, = VREF/2; CFG[12:10] = 0102. Unipolar differential with COM connected to a ground sense; CFG[12:10] = 1102. * Figure 14C, bipolar differential pairs with INx- referenced to VREF/2; CFG[12:10] = 00X2. Unipolar differential pairs with INx- referenced to a
5:3
REF
Rev. PrC | Page 13 of 20
-007
AD7689
ground sense; CFG[12:10] = 10X2. In this configuration, the IN+ is identified by the channel in CFG[9:7]. Example: for IN0 = IN1+ and IN1 = IN1-, CFG[9:7] = 0002; for IN1 = IN1+ and IN0 = IN1-, CFG[9:7] = 0012 * Figure 14D, sows the inputs configured in any of the above combinations as the AD7689 can be configured dynamically.
Preliminary Technical Data
more than 0.3 V because this causes the diodes to become forward biased and to start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer's supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part.
VDD IN+ OR INOR COM GND
-009
Sequencer
The AD7689 includes a channel sequencer useful for scanning channels in a IN0 to INn fashion. Channels are scanned as single or pairs and with or without the temperature sensor, after the last channel is sequenced. The sequencer starts with IN0 and finishes with INn set in CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that the channel pairs are always paired IN(even) = INx+ and IN(odd) = INx- regardless of CFG[7]. To enable the sequencer, CFG[2:1] are written to for initializing the sequencer. After CFG[13:0] is updated, DIN must be held low while reading data out (at least for bit 13) or the CFG will begin updating again. While operating in a sequence, the CFG can be changed by writing 012 to CFG[2:1]. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence will reinitialize and convert IN0 (or IN1) after CFG is updated. Examples (only bits for input and sequencer are highlighted) Scan all IN[7:0] referenced to COM = GND sense with temperature sensor:
13 CFG 12 1 11 10 INCC 1 0 87 INn 111 9 6 BW 5 43 REF 21 SEQ 10 0 RB -
D1 CPIN D2
RIN
CIN
Figure 15. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true differential signal between INn+ and COM or INn+ and INn-. By using these differential inputs, signals common to both inputs are rejected. During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 3.5k and is a lumped component made up of serial resistors and the on resistance of the switches. CIN is typically 27 pF and is mainly the ADC sampling capacitor.
Selectable Low Pass Filter
During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. While the AD7689 is acquiring, RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low pass filter can be programmed for the full bandwidth or 1/4 of the bandwidth with CFG[6] as shown in Table 9.
Scan 3 paired channels without temperature sensor and referenced to VREF/2:
13 CFG 12 0 11 10 INCC 0 X 9 87 INn 10X 6 BW 5 43 REF 21 SEQ 11 0 RB -
DRIVER AMPLIFIER CHOICE
Although the AD7689 is easy to drive, the driver amplifier needs to meet the following requirements: * The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7689. Note that the AD7689 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise coming from the amplifier is filtered by the AD7689 analog input circuit lowpass filter made by RIN and CIN or by an external filter, if one is used. Because the typical noise of the AD7689 is 35 V rms (with VREF = 5V), the SNR degradation due to the amplifier is
Scan 4 paired channels referenced to a GND sense with temperature sensor:
13 CFG 12 1 11 10 INCC 0 X 9 87 INn 11X 6 BW 5 43 REF 21 SEQ 10 0 RB -
Input Structure
Figure 15 shows an equivalent circuit of the input structure of the AD7689. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by
SNRLOSS
35 = 20log 2 2 35 + f -3dB (Ne N ) 2

Rev. PrC | Page 14 of 20
Preliminary Technical Data
where: f-3dB is the input bandwidth in MHz of the AD7689 (1.7MHz in full BW or 425kHz in 1/4 BW) or the cutoff frequency of an input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/Hz. * For ac applications, the driver should have a THD performance commensurate with the AD7689. TBD shows the AD7689's THD vs. frequency. * For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7689 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In the amplifier's data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
Table 10. Recommended Driver Amplifiers
Amplifier ADA4841-X AD8655 AD8021 AD8022 OP184 AD8605, AD8615 Typical Application Very low noise, small, and low power 5 V single supply, low noise Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low power
AD7689
the temperature sensor, the output is straight binary referenced from the AD7689 GND pin. The internal reference is temperature-compensated to within 15 mV. The reference is trimmed to provide a typical drift of 3 ppm/C. This typical drift characteristic is shown in TBD.
External Reference and Internal Buffer
For improved drift performance, and external reference can be used with the internal buffer. The external reference is connected to REFIN and the output is produced on the REF pin. There are two modes which can use en external reference with the internal buffer; one with the temperature sensor enabled and one without. Refer to Table 9 for the register details. With the buffer enabled, the gain us unity and limited to input/output of 4.096V. The internal reference buffer is useful in multi-converter applications since a buffer is typically required in these applications. Also, the use of a low power reference can be used since the internal buffer provides the necessary performance to drive the SAR architecture of the AD7689.
External Reference
In any of the six modes, an external reference can be connected directly on the REF pin since the output impedance of REF is > 5k ohms. To reduce power consumption, the reference and buffer can be powered down independently or together for the lowest power consumption. However, for applications requiring the use of the temperature sensor, the reference needs to be active. Refer to Table 9 for register details. For improved drift performance, an external reference such as the ADR43x or ADR44x is recommended.
When the source impedance of the driving circuit is low, the AD7689 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.
Reference Decoupling
Whether using an internal or external reference, the AD7689 voltage reference output/input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 22 F (X5R, 1206 size) ceramic chip capacitor is appropriate when using either the internal reference, the ADR43x /ADR44x external reference or from a low impedance buffer such as the AD8031 or the AD8605. The placement of the reference decoupling is also important to the performance of the AD7689, as explained in the Layout section. The decoupling capacitor should be mounted on the same side as the ADC right at the REF pin with a thick PCB trace. The GND should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. If desired, smaller reference decoupling capacitor values down to 2.2 F can be used with a minimal impact on performance, especially DNL.
VOLTAGE REFERENCE OUTPUT/INPUT
The AD7689 allows the choice of either a very low temperature drift internal voltage reference, an external reference or an external buffered reference. The internal reference of the AD7689 provides excellent performance and can be used in almost all applications. There are a possible 6 choices of voltage reference schemes briefly described in Table 9 with further details in each of the following sections.
Internal Reference/Temperature Sensor
The internal reference can be set for either 2.5V or a 4.096V output as detailed in Table 9. With the internal reference enabled, the band-gap voltage will also be present on the REFIN pin, which requires an external 0.1 F capacitor. Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7689 thus useful for performing a system calibration. Note that when using
Rev. PrC | Page 15 of 20
AD7689
Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. For applications that use multiple AD7689s or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage thus reducing SAR conversion crosstalk. The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a 15 ppm/C TC of the reference changes full-scale by 1 LSB/C.
Preliminary Technical Data
DIGITAL INTERFACE
The AD7689, uses a simple 4-wire interface and is compatible with SPI, QSPI, digital hosts, and DSPs, for example, Blackfin(R) ADSP-BF53x or ADSP-219x. The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversions, to be independent of the read back timing. This is useful in low jitter sampling or simultaneous sampling applications.
CFG Writing
Prior to conversion, the AD7689 needs the CFG written to unless the factory default setting is to be used as described in the beginning of the Configuration Register section. If DIN is high during the 1st SCK falling edge, CFG will be updated on the 14th falling SCK edge. After the 14th SCK, the CFG will be disabled and not accept any new CFG data until after the end of conversion, tCONV (max). The CFG must be updated before the end of conversion for the setting to take effect for the next conversion. It can also be updated while reading back data thus minimizing the SCK activity.
POWER SUPPLY
The AD7689 uses three power supply pins: two core supplies, VDD, and a digital input/output interface supply, VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7689 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range. The AD7689 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low batterypowered applications.
Conversion Data
The conversion data can be read at any time; during acquisition, during conversion and after conversion. While reading during conversion, the data read is from the previous conversion (n-1) as the current conversion (n) is active. The AD7689 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback. The BUSY indicator feature is enabled when the CNV is held low before the maximum conversion time, tCONV (max). Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, DIN) during the conversion. However, due to the possibility of performance degradation, digital activity should only occur prior to the minimum conversion time, tCONV (min) since the AD7689 provides error correction circuitry that can correct for an incorrect bit during this time. The user should configure the AD7689 and initiate the busy indicator (if desired) during this time. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 30 ns before and 10 ns after the rising edge of CNV. To this extent, it is recommended, to use a discontinuous SCK whenever possible to avoid any potential performance degradation.
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7689, with its low operating current, can be supplied directly using the reference circuit shown in Figure 16. The reference line can be driven by * * * The system power supply directly A reference voltage with enough current output capability, such as the ADR43x/ADR44x A reference buffer, such as the AD8031, which can also filter the system power supply, as shown in Figure 16
5V 5V 10 5V 10k 1F
AD8031
1
22F
1F
CAP
VDD
VIO
AD7689
REFERENCE BUFFER AND FILTER.
-010
1OPTIONAL
Figure 16. Example of an Application Circuit
Rev. PrC | Page 16 of 20
Preliminary Technical Data
WITHOUT BUSY INDICATOR
This mode is usually used when the AD7689 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 17, and the corresponding timing is given in Figure 18. A rising edge on CNV initiates a conversion and forces SDO to high impedance. Once a conversion is initiated, it continues until completion irrespective of the state of CNV. This could be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. Configuring the AD7689 for the (n + 1) conversion is initiated when SCK is high and a rising edge on CNV. After this mode is initiated, CNV is a don't care as the CFG word is written in MSB first with 14 SCK rising edges. As shown in Figure 18, CFG is written to during the current (n) conversion before the end of conversion, or tCONV minimum time. At the end of
AD7689
conversion, the register is updated. In this mode, the new configuration settings are used for the following (n + 1) acquisition and conversion. The AD7689 can also be configured on 14 SCKs of the data reading (not shown), thus reducing the number of SCK bursts. However, this new CFG setting is for the (n + 2) conversion since the (n) conversion has ended. This mode is useful when using multiple AD7689s using the same configuration. When the conversion is complete, the AD7689 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance.
CONVERT
DIGITAL HOST
CNV SDO DIN DATA IN CFG DATA
AD7689
SCK
CLK
Figure 17. Without Busy Indicator Connection Diagram
t CYC t CNVH
CNV
t CONV
ACQUISITION (n) CONVERSION (n)
-011
tACQ
ACQUISITION (n + 1) CONVERSION (n + 1)
tCSCK tSCKH
SCK 1 2 3 13 14 1 2 3 14
tSCK
15
16
tHDIN
DIN C13 C12 C11 C1 C0
tHSDO tDSDO tEN
D15 D14 D13
tSCKL
tSDIN
SDO
tDIS
D2 D1 D0
Figure 18. Without Busy Indicator Serial Interface Timing
Rev. PrC | Page 17 of 20
-012
AD7689
WITH BUSY INDICATOR
This mode is usually used when the AD7689 is connected to an SPI-compatible digital host using an interrupt input. The connection diagram is shown in Figure 19,, and the corresponding timing is given in Figure 20. A rising edge on CNV initiates a conversion and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. Configuring the AD7689 for the (n + 1) conversion is initiated when SCK is high and a rising edge on CNV. After this mode is initiated, CNV is a don't care as the CFG word is written in MSB first with 14 SCK rising edges. As shown in Figure 20, CFG is written to during the current (n) conversion before the end of conversion, or tCONV minimum time. At the end of conversion, the register is updated. In this mode, the new configuration settings are used for the following (n + 1)
VIO
Preliminary Technical Data
acquisition and conversion. Note that SCK must be high when CNV goes high for this configuration mode. The AD7689 can also be configured on the first 14 SCK of the data reading (not shown), thus reducing the number of SCK bursts. However, this new CFG setting is for the (n + 2) conversion. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7689 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. If multiple AD7689s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation.
CONVERT
DIGITAL HOST
CNV SDO DATA IN IRQ DIN CFG DATA
AD7689
SCK
CLK
Figure 19. With Busy Indicator Connection Diagram
t CYC t CONV (MIN)
CNV
t CONV (MAX)
ACQUISITION (n) CONVERSION (n)
-013
tACQ
ACQUISITION (n + 1) CONVERSION (n + 1)
tCSCK tSCKH
SCK 1 2 3 13 14 1 2 3 4 14
tSCK
15
16
17
tSDIN tHDIN
DIN C13 C12 C11 C1 C0
tHSDO tDSDO
tSCKL tDIS
SDO
-014
D15
D14
D13
D3
D2
D1
D0
Figure 20. Wwith Busy Indicator Serial Interface Timing
Rev. PrC | Page 18 of 20
Preliminary Technical Data APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7689 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7689, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7689 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7689s. The AD7689 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7689 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7689 and connected using short, wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. An example of a layout following these rules is shown in Figure 21 and Figure 22.
AD7689
Figure 21. Example Layout of the AD7689 (Top Layer) Figure 22. Example Layout of the AD7689 (Bottom Layer)
EVALUATING AD7689 PERFORMANCE
Other recommended layouts for the AD7689 are outlined in the documentation of the evaluation board for the AD7689 (EVAL-AD7689CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3Z.
Rev. PrC | Page 19 of 20
AD7689 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX
15 16 20
Preliminary Technical Data
0.60 MAX
PIN 1 INDICATOR
1
PIN 1 INDICATOR
3.75 BCS SQ
0.50 BSC
EXP OSED PAD
(BOTT OM VIEW)
5
2.65 2.50 SQ 2.35
TOP VIEW 0.80 MAX 0.65 TYP
0.50 0.40 0.30
11
10
6
0.25 MIN
1.00 0.85 0.80 SEATING PLANE
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 23. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 4 mm x 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters
ORDERING GUIDE
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07083-0-9/07(PrC)
Rev. PrC | Page 20 of 20
081407-B
0.30 0.23 0.18
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF

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